1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to data input/output pins and command and address input pins of a memory device.
2. Description of the Related Art
A conventional semiconductor memory device such as a DRAM includes address pins A, command pins C, and pins DQ via which data is input or output.
FIG. 1 is a schematic block diagram of a conventional memory device 100. The conventional memory device 100 includes a memory core 101, a write/read pipeline unit 103, a command and address decoder (command/address decoder) 105, a clock buffer 107, and an input/output (I/O) buffer 115. The I/O buffer 115 includes a data input buffer 109, a command and address input buffer 111, and a data output buffer 113. The I/O buffer 115 further includes a plurality of command and address input pins 117 connected to the command and address (command/address) input buffer 111, chip selection (CS) pins 119 connected to the command and address decoder 105, data I/O (DQ) pins 121 connected to the data input buffer 109 and the data output buffer 115, and a clock input (CLK) pin 123 through which a clock signal is input to the conventional memory device 100.
In the conventional memory device 100, the command and address input pins (command/address pins) 117 are separated from the data input pins 121. That is, the command and address input pins 117 are used to receive and transmit only external command and address signals, and the data I/O pins 121 are used to receive and output only data.
As illustrated in FIG. 1, the conventional memory device 100 selectively performs exclusively a read operation or a write operation at a specific instant in time. That is, the conventional memory device 100 is not capable of receiving data simultaneously with outputting data via the data I/O pins 121 at a specific instant in time.
Of course, both the read and write operations can be simultaneously performed in response to a proper combination of commands in the conventional memory device 100. However, since inputting of data to the I/O pins 121 for the read operation is not performed concurrently with outputting of data from the data I/O pins 121 for the read operation, the write operation must be performed following the read operation, or the read operation must be performed following the write operation. In other words, the data I/O pins 121 experience a time gap between the write operation and the read operation during which they are dormant. In the conventional memory device 100, after one of the read operation and the write operation is completed, the other can be performed, and thus, the switching between read and write operations can have a negative effect on data processing speed and overall system efficiency.
To increase the speed of inputting/outputting data, it has been suggested that the data I/O pins DQ be divided into data input pins D and data output pins Q and that they be configured independently of each other so as to receive and output data via different pins. In this case, since data is received and output using different signal lines, the time difference between data input and data output operations is reduced, thereby enabling the memory device 100 to very effectively process the data. However, since all command and address input pins, data output pins, and data input pins are required, that is, a large number of pins are required, such a configuration leads to semiconductor module design problems owing to the high pin count.